fsl-layerscape: Consolidate registers space defination for CCI-400 bus

fsl-layerscape: Consolidate registers space defination for CCI-400 bus

CoreLink Cache Coherent Interconnect (CCI) provides full cache
coherency between two clusters of multi-core CPUs and I/O coherency
for devices and I/O masters.

This patch add new config option SYS_FSL_HAS_CCI400 and moves
existing register space definaton of CCI-400 bus to fsl_immap to be
shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET
in Kconfig.

Signed-off-by: Ashish Kumar <[email protected]>
Signed-off-by: Prabhakar Kushwaha <[email protected]>
[YS: revised commit message, squashed patches for armv8 and armv7]
Reviewed-by: York Sun <[email protected]>